Gate-and-switch-level modeling

1、verilog-std-1364-2005¹

There are 14 logic gates and 12 switches predefined in the Verilog HDL to provide the gate- and switch-level modeling facility. Modeling with logic gates and switches has the following advantages:

— Gates provide a much closer one-to-one mapping between the actual circuit and the model.
— There is no continuous assignment equivalent to the bidirectional transfer gate.

Verilog1364-2005标准规定了26个基本原件，其中14个门级原件，12个开关级原件。

对于这些原件不需要定义直接调用。

2、门级建模²

1. 多输入门：

   n_input_gate_instance ::= [ name_of_gate_instance ] 
   ( output_terminal , input_terminal { , input_terminal } ) 
   
   and A1(out1, in1, in2);
   or  O1(outa, inb, inc, ind);
   xor X1(outx, inx, iny, inz, inw);

2. 多输出门调用:

   n_output_gate_instance ::= [ name_of_gate_instance ] 
   ( output_terminal { , output_terminal } , input_terminal ) 
   
   buf BUF_1(bufout1, bufout2, bufout3, bufin);
   not NOT_1(out1, out2, in);

3. 三态门调用:

   enable_gate_instance ::= [ name_of_gate_instance ] 
   ( output_terminal , input_terminal , enable_terminal )
   
   bufif1 BF1(data_bus, data, enable);

4. 二个电阻

   The instance declaration of a pullup or a pulldown source shall begin with one of the following keywords: pullup , pulldown

   pull_gate_instance ::= [ name_of_gate_instance ] ( output_terminal )  
   
   pullup   (strong1)  p1 (neta), p2 (netb);
   
   In this example, the  p1  instance drives  neta  and the  p2  instance drives netb  with strong strength.

5. 注意: 门级原件的端口列表都固定好了，可以不用定义中间连接信号类型(wire)

   ---

示例：

// 门级建模实现最小项表达式
// F(a, b, c) = m1 + m2 + m3 + m6 + m7 = (!a)c + b
module zuixiaoxiang(out, a, b, c);
    input a, b, c;
    output out;
    wire s1, s2;
    not U1(s1, a);
    and U2(s2, s1, c);
    or U3(out, s2, b);
endmodule

3、开关级建模

1. MOS switches

cmos	pmos	nmos
rcmos	rnmos	rpmos

rmos : 代表晶体管导通时源漏有较高的阻抗(impedance)

The following example declares a pmos switch:

pmos  p1 (out, data, control);

The output is  out , the data input is  data , and the control input is 
control.The instance name is  p1 .

1. Bidirectional pass switches(双向开关)

tran	tranif1	tranif0
rtran	rtranif1	rtranif0

The bidirectional pass switches shall not delay signals propagating through them. When tranif0, tranif1,rtranif0, or rtranif1 devices are turned off, they shall block signals; and when they are turned on, they shall pass signals. The tran and rtran devices cannot be turned off, and they shall always pass signals.(双向开关没有传播延时)

The following example declares an instance of tranif1:

tranif1  t1 (inout1,inout2,control);

The bidirectional terminals are  inout1  and  inout2 . The control input is  control . The instance name is t1 .

示例：

// 2输入与门
// time:2020-04-05
module and2_1(out, a, b);
    input a,b;
    output out;
    wire s1, s2;
    supply0 Gnd;
    supply1 Vdd;
    pmos U1(s1, Vdd, a);
    pmos U2(s1, Vdd, b);
    nmos U3(s1, s2, a);
    nmos U4(s2, Gnd, b);
    pmos U5(out, Vdd, s1);
    nmos U6(out, Gnd, s1);
endmodule

quarter II 综合不了，没办法直接看viewer。只能把书上的图扒来了。

---

终于找到了一款RTL级，gate级，开关级debugger和viewer的软件

trainsistor-level debugger and viewer

但是目前下载不了，得找客服联系。不知有人有用过这款软件没有。有的话请你一定告诉我。

Renference

[1] verilog-std-1364-2005

[2] 蔡觉平.2015.Verilog HDL 数字集成电路高级程序设计 31P