Preface

Generate constructs are used to either conditionally or multiply instantiate generate blocks into a model

生成结构用于要么有条件地或成倍地实例化生成块到一个模型中。

有两种生成结构：loops和conditionals

loops: 用于实例生成块多次

conditionals: 包括if-generate和case-generate结构;最多从一系列generate blocks中选择一个.

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Generate schemes are evaluated during elaboration of the model.

生成方法：决定哪个生成块被实例化或多少生成块被实例化的方法。

Elaboration occurs after parsing the HDL and before simulation(生成发生在解析HDL之后仿真之前);包括如下五个过程：

• expanding module instantiations
• computing parameter values
• resolving hierarchical names
• establishing net connectivity
• preparing the model for simulation

Loop generate constructs

loop生成结构运行使用类似for loop 的语法把一个生成块实例多次。循环索引变量应该在使用前用genvar声明；genvar只在elaboration时有用，所以你不能在生成块任何地方引用它。

1. 参数化

   module  gray2bin1 (bin, gray); 
      parameter  SIZE = 8;      // this module is parameterizable 
      output  [SIZE-1:0] bin; 
      input   [SIZE-1:0] gray; 
     
      genvar  i; 
      generate  
        for  (i=0; i<SIZE; i=i+1)  begin :bit
          assign  bin[i] = ^gray[SIZE-1:i]; 
               // i refers to the implicitly defined localparam whose
               // value in each instance of the generate block is
               // the value of the genvar when it was elaborated.
        end 
      endgenerate
   endmodule

2. 使用二维net把生成的实例连接起来

   module  addergen1 (co, sum, a, b, ci); 
      parameter  SIZE = 4; 
      output  [SIZE-1:0] sum; 
      output             co; 
      input   [SIZE-1:0] a, b; 
      input              ci; 
      wire    [SIZE  :0] c; 
      wire    [SIZE-1:0] t [1:3]; 
      genvar             i; 
     
      assign  c[0] = ci; 
     
     // Hierarchical gate instance names are: 
     // xor gates: bit[0].g1 bit[1].g1 bit[2].g1 bit[3].g1
     //            bit[0].g2 bit[1].g2 bit[2].g2 bit[3].g2
     // and gates: bit[0].g3 bit[1].g3 bit[2].g3 bit[3].g3
     //            bit[0].g4 bit[1].g4 bit[2].g4 bit[3].g4
     // or  gates: bit[0].g5 bit[1].g5 bit[2].g5 bit[3].g5 
     // Generated instances are connected with 
     // multidimensional nets t[1][3:0] t[2][3:0] t[3][3:0] 
     // (12 nets total) 
      
        for (i=0; i<SIZE; i=i+1)  begin :bit
          xor  g1 ( t[1][i],    a[i],    b[i]); 
          xor  g2 (  sum[i], t[1][i],    c[i]); 
          and  g3 ( t[2][i],    a[i],    b[i]); 
          and  g4 ( t[3][i], t[1][i],    c[i]); 
          or   g5 (  c[i+1], t[2][i], t[3][i]); 
        end  
     
      assign  co = c[SIZE]; 
   endmodule

3. multilevel generate loop

   parameter  SIZE = 2; 
   genvar  i, j, k, m; 
   generate  
      for  (i=0; i<SIZE; i=i+1)  begin :B1     // scope B1[i] 
       M1 N1();                   // instantiates B1[i].N1
        for  (j=0; j<SIZE; j=j+1)  begin :B2   // scope B1[i].B2[j]
         M2 N2();                 // instantiates B1[i].B2[j].N2 
          for  (k=0; k<SIZE; k=k+1)  begin :B3 // scope B1[i].B2[j].B3[k] 
           M3 N3();               // instantiates B1[i].B2[j].B3[k].N3
          end  
        end  
        if  (i>0)  begin :B4                   // scope B1[i].B4
          for  (m=0; m<SIZE; m=m+1)  begin :B5 // scope B1[i].B4.B5[m] 
           M4 N4();               // instantiates B1[i].B4.B5[m].N4 
          end  
        end
      end  
   endgenerate  
     // Some examples of hierarchical names for the module instances: 
     // B1[0].N1              B1[1].N1
     // B1[0].B2[0].N2        B1[0].B2[1].N2
     // B1[0].B2[0].B3[0].N3  B1[0].B2[0].B3[1].N3
     // B1[0].B2[1].B3[0].N3
     // B1[1].B4.B5[0].N4     B1[1].B4.B5[1].N4

   Conditional generate constructs

条件生成结构只能选择一个生成块

module  test;
parameter  p = 0, q = 0;
wire  a, b, c;
//---------------------------------------------------------
// Code to either generate a u1.g1 instance or no instance.
// The u1.g1 instance of one of the following gates:
// (and, or, xor, xnor) is generated if
// {p,q} == {1,0}, {1,2}, {2,0}, {2,1}, {2,2}, {2, default}
//---------------------------------------------------------
if  (p == 1)
   if  (q == 0)
     begin  : u1          // If p==1 and q==0, then instantiate
       and  g1(a, b, c); // AND with hierarchical name test.u1.g1
     end
   else   if  (q == 2)
     begin  : u1          // If p==1 and q==2, then instantiate
       or   g1(a, b, c); // OR with hierarchical name test.u1.g1
     end
                   // "else" added to end "if (q == 2)" statement
   else ;                                   // If p==1 and q!=0 or 2, then no instantiation
else   if  (p == 2)
   case  (q)
  0, 1, 2:
     begin  : u1         // If p==2 and q==0,1, or 2, then instantiate
            xor  g1(a, b, c);// XOR with hierarchical name test.u1.g1
          end
   default :
     begin  : u1          // If p==2 and q!=0,1, or 2, then instantiate
       xnor  g1(a, b, c);// XNOR with hierarchical name test.u1.g1
     end
   endcase
endmodule

External names for unnamed

尽管一个没有名字的生成块没有可以被使用的阶级名字(hierarchical name)，但是它需要一个名字让外部接口可以访问它。因此出于该目的将会给他们分配名字。

所有没名字的生成块将被给予genblk<n>名字,其中是被分配到它包括的生成结构的次数。（从1开始计数）；如果有冲突,在前面加0直到不冲突为止

module  top;
   parameter  genblk2 = 0;
   genvar  i;
  // The following generate block is implicitly named genblk1
   if  (genblk2)  reg  a;  // top.genblk1.a
   else                    reg  b;  // top.genblk1.b
  // The following generate block is implicitly named genblk02
  // as genblk2 is already a declared identifier
   if  (genblk2)  reg  a;  // top.genblk02.a
   else                    reg  b;  // top.genblk02.b
  // The following generate block would have been named genblk3 
  // but is explicitly named g1
   for  (i = 0; i < 1; i = i + 1)  begin  : g1    // block name
    // The following generate block is implicitly named genblk1 
    // as the first nested scope inside of g1
     if  (1)      reg  a;  // top.g1[0].genblk1.a
   end
  // The following generate block is implicitly named genblk4 since 
  // it belongs to the fourth generate construct in scope "top". 
  // The previous generate block would have been 
  // named genblk3 if it had not been explicitly named g1
   for  (i = 0; i < 1; i = i + 1)
    // The following generate block is implicitly named genblk1 
    // as the first nested generate block in genblk4
     if  (1)      reg  a;  // top.genblk4[0].genblk1.a
  
  // The following generate block is implicitly named genblk5
   if  (1)        reg  a;  // top.genblk5.a
endmodule